This invention relates to a vernier-type absolute encoder and in particular to a vernier-type absolute encoder concerning signal processing in absolute value signal generation and input signals (phase signal and phase difference signal) and in particular to an absolute encoder hard to be affected by a phase error between slit strings caused by distortion of a detection waveform or the like in simple operation processing and adaptable to high-speed rotation.
In general, a vernier-type absolute encoder in a related art generates phase difference signals from two pairs of phase signals, determines the pitch number of a shorter-pitch phase difference signal from a longer-pitch phase difference signal, repeats this process in order, and last determines the pitch number of the phase signal of the largest number of pitches.
FIG. 13 is a schematic representation of the operation of an absolute encoder in a related art. As shown here, if the pitch length of a phase difference signal is 4:1, the relation between phase predicted value xcfx86bxe2x80x2 and pitch number predicted value N of a short-pitch phase difference signal in phase xcfx86a of a long-pitch phase difference signal is
xcfx86bxe2x80x2=4xcfx86axe2x88x922Nxcfx80
where N is found as a value of 0 less than xcfx86bxe2x80x2 less than 2 xcfx80 among 0, 1, 2, and 3.
Next, the pitch number is determined from xcfx86b actually obtained.
If the pitch number predicted value is 1 and xcfx86bxe2x80x2 less than xcfx80 as in FIG. 13,
(1) when 0 less than xcfx86b less than xcfx86bxe2x80x2+xcfx80, the pitch number is determined 1 equal to the predicted value; or
(2) when xcfx86bxe2x80x2+xcfx80 less than xcfx86b less than 2 xcfx80, the pitch number is determined 0 resulting from subtracting 1 from the predicted value.
In such a method, if the phase error between the signals is, in the example, theoretically within xc2x1xcfx80/4 (which becomes xc2xd resulting from dividing 2 xcfx80 by pitch rate 4) in terms of angle represented by the phase angle of xcfx86a, the pitch number can be determined correctly.
In fact, the following processing is performed for the digital phase difference signals:
Letting xcfx86a and xcfx86b be a four-bit (t3, t2, t1, t0) signal and a four-bit (s3, s2, s1, s0) signal respectively, first a tentative pitch number (pitch number predicted value) is determined based on the high-order two bits of xcfx86a.
The tentative pitch number becomes as follows:
When the high-order two bits (t3, t2) of xcfx86a are
(0, 0): 0
(0, 1): 1
(1, 0): 2
(1, 1): 3.
For example, if the bit string of xcfx86a, (t3, t2, t1, t0), is (0, 1, 0, 0), the pitch number predicted value becomes 1.
Next, the low-order two bits (t1, t0) of xcfx86a are compared with the high-order two bits (s3, s2) of xcfx86b, whereby the tentative pitch number is corrected and the pitch number of xcfx86b is determined finally.
The correction of the pitch number will be discussed by taking a case where the low-order two bits (t1, t0) of xcfx86a are (0, 0) as an example.
If the high-order two bits (s3, s2) of xcfx86b are
(1) (0, 0) or (0, 1), the pitch number is determined 1 equal to the predicted value;
(2) (1, 1), the pitch number is determined 0 resulting from subtracting 1 from the predicted value. (3) However, if the high-order two bits are (1, 0), the error from the predicted value becomes equal when the pitch number 1 or 0, and the pitch number cannot be determined.
There is a possibility that the state of (3) will be entered if the phase error between xcfx86a and xcfx86b becomes equal to or greater than xcfx80/8 in terms of angle represented by the phase angle of xcfx86a; it is seen that the pitch number cannot be determined. In this example, the allowance of the phase error becomes a half that under an ideal condition.
However, in the above-described example in the related art, the following problem is involved: To determine the pitch number of a short-pitch phase difference signal from a long-pitch phase difference signal, a determination processing function of a computing element (microprocessor), etc., is required.
There is a condition under which the pitch number cannot be determined, thus the allowance of the phase error between the signals lessens.
If the number of bits involved in signal processing is few, the allowance of the phase error lessens; if the number of bits involved in processing is increased to grow the allowance of the phase error and bring the condition close to the ideal condition, operation processing becomes complicated. This is a problem.
It is therefore an object of the invention to provide a low-cost, high-reliability absolute encoder hard to be affected by a phase error between slit strings caused by distortion of a detection waveform or the like by performing simple operation processing without requiring a determination processing function of a computing element, etc.
To the end, according to an aspect of the invention, there is provided an absolute encoder comprising a scale having a plurality of tracks different in the number of pitches where position information repeated at the same pitches is formed, a plurality of sensors for making a relative move to the scale for detecting the position information, a phase modulation section for converting signals from the sensors into phase signals, a digital conversion section for converting the phase signals and each phase difference signal between two arbitrary phase signals into digital signals, and an absolute value signal generation section for generating a signal concerning an absolute position based on the digitized phase signals and the digitized phase difference signals, characterized in that
when the phase signals xcfx860, xcfx861, xcfx862, xcfx863 . . . are j-bit digital signals represented as
xcfx860=2xcfx80a0x+b0
xcfx861=2xcfx80a1x+b1
xcfx862=2xcfx80a2x+b2
xcfx863=2xcfx80a3x+b3
. . .
where a0, a1, a2, a3, . . . are each the number of pitches, x is relative displacement between scale and sensor, b0, b1, b2, b3, . . . are each an initial phase,
the absolute value signal generation section sets the numbers of pitches a0, a1, a2, a3 . . . so that
the number of pitches of phase difference signal xcfx8601 between xcfx860 and xcfx861 (a0xe2x88x92a1),
the number of pitches of phase difference signal xcfx8602 between xcfx860 and xcfx862 (a0xe2x88x92a2),
the number of pitches of phase difference signal xcfx8603 between xcfx860 and xcfx863 (a0xe2x88x92a3)
. . .
become
a0/(a0xe2x88x92a1)=2K1 
(a0xe2x88x92a1)/(a0xe2x88x92a2)=2K2 
(a0xe2x88x92a2)/(a0xe2x88x92a3)=2K3 
. . .
where k1, k2, k3 . . . are each an integer,
an absolute value signal A01 of the number of pitches (a0xe2x88x92a1) can be generated in such a way that the high-order k1 bits of the signal A01 is that of the signal provided by subtracting the signal that is provided by dividing xcfx860 by 2K1 from xcfx8601 whereas the low-order bits of the signal A01 is xcfx860. Next, an absolute value signal A02 of the number of pitches (a0xe2x88x92a2) can be generated in such a way that the high-order k2 bits of the signal A02 is that of the signal provided by subtracting the signal that is provided by dividing A01 by 2K2 from xcfx8602 whereas the low-order bits is A01. Executing these processes in order can generate a longer-pitch absolute value signal.
Specifically, positions of the position information on the scale are formed or a phase adjustment circuit is provided so that a phase xcfx80 point of xcfx860 becomes a phase zero point of xcfx8601, that a phase xcfx80 point of A01 becomes a phase zero point of xcfx8602, and that a phase xcfx80 point of A02 becomes a phase zero point of xcfx8603.
More specifically, the phase adjustment circuit inputs a phase adjustment signal into a shift register, generates a plurality of phase adjustment signals different in shift amount with that phase adjustment signal shifted in order based on an adjustment reference clock, selects each post-shifted phase adjustment signal by a multiplexer, generates a carrier wave from the selected signal, and inputs the carrier wave into phase modulation section for making a phase adjustment of the phase signal.
According to another aspect of the invention, there is provided an absolute encoder comprising a scale having a plurality of tracks different in the number of pitches where position information repeated at the same pitches is formed, a plurality of sensors for making a relative move to the scale for detecting the position information, a phase modulation section for converting signals from the sensors into phase signals, a digital conversion section for converting the phase signals and each phase difference signal between two arbitrary phase signals into digital signals, and an absolute value signal generation section for generating a signal concerning an absolute position based on the digitized phase signals and the digitized phase difference signals, characterized in that the digital conversion section inputs the phase signal into a PLL, (phase-locked loop) circuit, generates a clock whose frequency is changed in association with a period of the phase signal by the PLL circuit, and generates the phase difference signal based on the count of the clocks.
According to yet another aspect of the invention, there is provided an absolute encoder comprising a scale having a plurality of tracks different in the number of pitches where position information repeated at the same pitches is formed, a plurality of sensors for making a relative move to the scale for detecting the position information, a phase modulation section for converting signals from the sensors into phase signals, a digital conversion section for converting the phase signals and each phase difference signal between two arbitrary phase signals into digital signals, and an absolute value signal generation section for generating a signal concerning an absolute position based on the digitized phase signals and the digitized phase difference signals, characterized in that the phase modulation section has a phase modulation circuit for inputting the phase signal corresponding to an arbitrary sensor signal into a PLL (phase-locked loop) circuit and modulating a carrier wave generated by the PLL circuit based on another sensor signal, thereby generating phase difference signal.
According to the described absolute encoder, it is required to determine the pitch number of a short-pitch phase signal using a long-pitch phase difference signal. For examples, when a phase signal xcfx8601, being changed in a sawtooth-shape signal having 0-2 xcfx80 levels in accordance with a position change at 128-pitch, is used as a short-pitch sawtooth signal, and a second phase difference signal xcfx8601, being changed in a sawtooth-shape signal having 0-2 xcfx80 levels in accordance with a position change at 128xe2x88x9296=32 pitch, is used as a long-pitch sawtooth signal, under such a conditions, a quarter-level signal provided by dividing a 128-pitch phase difference signal xcfx860 by 2K1 (for example, K1=2) is provided, and subtraction is made between said signal and the long-pitch phase difference signal so that a stepwise position detection signal formed by said subtraction has four steps (the number of pitches of short-pitch signal contained in one pitch of a long-pitch signal) to be four levels, and the period corresponding to one pitch of the short-pitch signal becomes a flat level.
If the phase zero point of the long-pitch signal is matched with the phase xcfx80 point of the short-pitch signal, the four levels of the stepwise signal formed by the subtracting become a middle of the level of the signal consisting of the high-order two bits of that signal and if some fluctuation occurs between both the signals, the signal of the high-order two bits does not change.
Therefore, the two-bit signal can be used to identify the four-pitch position of the short pitch signal in one pitch of the long-pitch signal. The identified signal becomes a 32-pitch signal with the same pitch as the long-pitch signal. Next, a longer-pitch signal is used to identify the 32-pitch signal. Thus, an absolute value signal can be generated by performing simply operation processing of only bit manipulation without requiring any complicated determination function. A large allowance of a phase error between short and long pitches can be taken.
The function capable of electrically shifting the phase of a phase signal using the phase adjustment circuit is provided, whereby the phase error caused by a mechanical error such as a slit work accuracy error or a sensor installation error can be absorbed and corrected for the phase conditions between the slit strings.
The PLL circuit is used to generate a clock whose frequency changes in association with a phase signal and the clock is used to digitize a phase difference signal, whereby a phase difference signal error can be prevented from occurring even at the high-speed disk rotation time.
To generate a phase difference signal between two sensor signals, a carrier wave having a fixed frequency is phase-modulated by a sensor signal of one of the two sensors, the PLL circuit is used to generate a carrier wave whose period changes in association with the phase-modulated signal, and the carrier wave is further phase-modulated by a sensor signal of the other sensor, whereby a phase difference signal not affected by the disk rotation speed can be generated. Therefore, an absolute encoder adaptable to high-speed rotation can be provided.